Skip navigation
Please use this identifier to cite or link to this item: https://libeldoc.bsuir.by/handle/123456789/33699
Full metadata record
DC FieldValueLanguage
dc.contributor.authorZalivako, S. S.-
dc.contributor.authorIvaniuk, A. A.-
dc.contributor.authorChang, C. H.-
dc.date.accessioned2018-12-04T13:13:00Z-
dc.date.available2018-12-04T13:13:00Z-
dc.date.issued2019-
dc.identifier.citationZalivaka, S. S. Reliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Response / S. S. Zalivaka, A. A. Ivaniuk, C. H. Chang // IEEE Transactions on Information Forensics and Security. – 2019. – №4(14). – P. 1109 – 1123. - DOI : 10.1109/TIFS.2018.2870835.ru_RU
dc.identifier.urihttps://libeldoc.bsuir.by/handle/123456789/33699-
dc.description.abstractField programmable gate array (FPGA) is a potential hotbed for malicious and counterfeit hardware infiltration. Arbiter-based physical unclonable function (A-PUF) has been widely regarded as a suitable lightweight security primitive for FPGA bitstream encryption and device authentication. Unfortunately, the metastability of flip-flop gives rise to poor A-PUF reliability in FPGA implementation. Its linear additive path delays are also vulnerable to modeling attacks.ru_RU
dc.language.isoenru_RU
dc.publisherInstitute of Electrical and Electronics Engineers (IEEE)ru_RU
dc.subjectпубликации ученыхru_RU
dc.subjectArbiter PUFru_RU
dc.subjectreliability enhancementru_RU
dc.subjectmachine learning attack resistanceru_RU
dc.subjectauthentication protocolru_RU
dc.titleReliable and Modeling Attack Resistant Authentication of Arbiter PUF in FPGA Implementation With Trinary Quadruple Responseru_RU
dc.typeСтатьяru_RU
Appears in Collections:Публикации в зарубежных изданиях

Files in This Item:
File Description SizeFormat 
Zalivaka_Reliable.pdf73.82 kBAdobe PDFView/Open
Show simple item record Google Scholar

Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.