Please use this identifier to cite or link to this item:
https://libeldoc.bsuir.by/handle/123456789/36689
| Title: | Project verification and construction of superchip tests at the RTL level |
| Authors: | Zolotorevich, L. A. |
| Keywords: | публикации ученых;Remote Control;Boolean Function;Test Design;Program Code;Permission Function |
| Issue Date: | 2013 |
| Publisher: | Pleiades Publishing |
| Citation: | Zolotorevich, L. A. Project verification and construction of superchip tests at the RTL level / L. A. Zolotorevich // Automation and Remote Control. – 2013. – Vol. 74, Issue 1. – PP. 113 – 122. – DOI: 10.1134/S0005117913010104. |
| Abstract: | Methods were proposed for project verification and directed design of the superchip
tests represented in VHDL at the RTL level. The problem of test design and project verification
was solved on the basis of the CNF-satisfiability of some system of Boolean functions. |
| URI: | https://libeldoc.bsuir.by/handle/123456789/36689 |
| Appears in Collections: | Публикации в зарубежных изданиях
|
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