| DC Field | Value | Language |
|---|
| dc.contributor.author | Rybenkov, E. V. | - |
| dc.contributor.author | Petrovsky, N. A. | - |
| dc.date.accessioned | 2020-12-14T12:49:57Z | - |
| dc.date.available | 2020-12-14T12:49:57Z | - |
| dc.date.issued | 2020 | - |
| dc.identifier.citation | Rybenkov, E. V. High performance multiplier-less pipelined FPGA architecture for 2-D non-separable quaternionic filter banks / E. V. Rybenkov, N. A. Petrovsky // Signal Processing: Algorithms, Architectures, Arrangements, and Applications : the 24th signal processing conference, Poznan, 23–25 september 2020 / Poznan University of Technology. – Poznan, 2020. – P. 42–47. – DOI: 10.23919/SPA50552.2020.9241273. | ru_RU |
| dc.identifier.uri | https://libeldoc.bsuir.by/handle/123456789/41687 | - |
| dc.description.abstract | This paper presents a systematic design of the 2-D non-separable quaternionic paraunitary filter banks (Q−PUFB) based on the integer-to-integer invertible quaternionic multiplier applied to image processing. | ru_RU |
| dc.language.iso | en | ru_RU |
| dc.publisher | Poznan University of Technology | ru_RU |
| dc.subject | публикации ученых | ru_RU |
| dc.subject | quaternionic paraunitary filter | ru_RU |
| dc.subject | non-separable transform | ru_RU |
| dc.title | High performance multiplier-less pipelined FPGA architecture for 2-D non-separable quaternionic filter banks | ru_RU |
| dc.type | Статья | ru_RU |
| Appears in Collections: | Публикации в зарубежных изданиях
|
