Metallization of Vias in Silicon Wafers to Produce Three-Dimensional Microstructures

Abstract

The processes of electrochemical deposition into a matrix of vertical vias of different diameters (500–2000 nm) in Si/SiO2 substrates with a TiN barrier layer at the bottom of the holes are studied. Morpho- logical studies of the metal in the holes show that the structure of copper clusters is rather uniform and is formed from crystallites of ~30 to 50 nm. Repeatability and stability with a homogeneous structure and with holes filled 100% by Cu determine the prospect of using the Si/SiO2/Cu system as a basic element for creating three-dimensional micro- and nanostructures, as well as for the 3D assembly of IC crystals.