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Please use this identifier to cite or link to this item: https://libeldoc.bsuir.by/handle/123456789/28888
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dc.contributor.authorPetrovsky, N. A.-
dc.contributor.authorRybenkov, E. V.-
dc.contributor.authorPetrovsky, A. A.-
dc.date.accessioned2017-12-28T07:36:47Z-
dc.date.available2017-12-28T07:36:47Z-
dc.date.issued2017-
dc.identifier.citationPetrovsky, N. A. Embedded distributed arithmetic based quaternions multiplier of paraunitary filter bank for lossless-to-lossy image coding / N. A. Petrovsky, E. V. Rybenkov, A. A. Petrovsky // Microprocessors and Microsystems. – 2017. - Vol.52. - Рp. 510 - 522.ru_RU
dc.identifier.urihttps://libeldoc.bsuir.by/handle/123456789/28888-
dc.description.abstractThis paper presents a systematic design of the integer-to-integer invertible quaternionic multiplier based on the block-lifting structure and pipelined embedded processor of the given multiplier using distributed arithmetic (DA) as a block of M-band linear phase paraunitary filter banks (LP PUFB) based on the quater- nionic algebra (Q-PUFB) for the lossy-to-lossless image coding. A bank Q-PUFB based on the DA block- lifting structure reduces the number of rounding operations and has a regular layout. Since the block-lifting structures with rounding operations can implement the integer-to-integer transform (Int-Q-PUFB).ru_RU
dc.language.isoenru_RU
dc.publisherElsevierru_RU
dc.subjectпубликации ученыхru_RU
dc.subjectquaternionru_RU
dc.subjectfilter bankru_RU
dc.subjectdistributed arithmeticru_RU
dc.subjectFPGA Embedded processorru_RU
dc.titleEmbedded distributed arithmetic based quaternions multiplier of paraunitary filter bank for lossless-to-lossy image codingru_RU
dc.typeСтатьяru_RU
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