DC Field | Value | Language |
dc.contributor.author | Petrovsky, N. A. | - |
dc.contributor.author | Rybenkov, E. V. | - |
dc.contributor.author | Petrovsky, A. A. | - |
dc.date.accessioned | 2017-12-28T07:36:47Z | - |
dc.date.available | 2017-12-28T07:36:47Z | - |
dc.date.issued | 2017 | - |
dc.identifier.citation | Petrovsky, N. A. Embedded distributed arithmetic based quaternions multiplier of paraunitary filter bank for lossless-to-lossy image coding / N. A. Petrovsky, E. V. Rybenkov, A. A. Petrovsky // Microprocessors and Microsystems. – 2017. - Vol.52. - Рp. 510 - 522. | ru_RU |
dc.identifier.uri | https://libeldoc.bsuir.by/handle/123456789/28888 | - |
dc.description.abstract | This paper presents a systematic design of the integer-to-integer invertible quaternionic multiplier based on the block-lifting structure and pipelined embedded processor of the given multiplier using distributed arithmetic (DA) as a block of M-band linear phase paraunitary filter banks (LP PUFB) based on the quater- nionic algebra (Q-PUFB) for the lossy-to-lossless image coding. A bank Q-PUFB based on the DA block- lifting structure reduces the number of rounding operations and has a regular layout. Since the block-lifting structures with rounding operations can implement the integer-to-integer transform (Int-Q-PUFB). | ru_RU |
dc.language.iso | en | ru_RU |
dc.publisher | Elsevier | ru_RU |
dc.subject | публикации ученых | ru_RU |
dc.subject | quaternion | ru_RU |
dc.subject | filter bank | ru_RU |
dc.subject | distributed arithmetic | ru_RU |
dc.subject | FPGA Embedded processor | ru_RU |
dc.title | Embedded distributed arithmetic based quaternions multiplier of paraunitary filter bank for lossless-to-lossy image coding | ru_RU |
dc.type | Статья | ru_RU |
Appears in Collections: | Публикации в зарубежных изданиях
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