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Please use this identifier to cite or link to this item: https://libeldoc.bsuir.by/handle/123456789/28892
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dc.contributor.authorPetrovsky, N. A.-
dc.contributor.authorRybenkov, E. V.-
dc.contributor.authorPetrovsky, A. A.-
dc.date.accessioned2017-12-28T11:45:55Z-
dc.date.available2017-12-28T11:45:55Z-
dc.date.issued2017-
dc.identifier.citationPetrovsky, N. A. Design and implementation of reversible integer quaternionic paraunitary filter banks on adder-based distributed arithmetic / N. A. Petrovsky, E. V. Rybenkov, A. A. Petrovsky // Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA’2017): Proc. 21st Int. Conf., Poznan, Poland, September 20-22, 2017 / Poznan University of Technology. – Poznan : IEEE, 2017. – P. 17 - 22.ru_RU
dc.identifier.urihttps://libeldoc.bsuir.by/handle/123456789/28892-
dc.description.abstractThis paper presents a design method of reversible integer quaternionic paraunitary filter banks (Int-Q-PUFB) using the adder-based distributed arithmetic (DAΣ) for implementation multiplier block-lifting structure modules. The proposed quaternion multiplier (Q-MUL) and 8-channel Int-Q-PUFB processors are implemented on the FPGA Xilinx Zynq 7010. The total magnitude response of analysis-synthesis system based on the given Int-Q-PUFB shows that the 8-channel 8 × 24 Int-Q-PUFB is perfect reconstruction filter bank for finite precision. Compared to known solutions of Int-Q-PUFB using block-lifting structure based on the CORDIC devices and ROM-based distributed arithmetic the given DAΣ-based Int-Q-PUFB have more less implementation complexity and latency.ru_RU
dc.language.isoenru_RU
dc.publisherIEEEru_RU
dc.subjectпубликации ученыхru_RU
dc.subjectquaternionru_RU
dc.subjectfilter bankru_RU
dc.subjectL2L image codingru_RU
dc.titleDesign and implementation of reversible integer quaternionic paraunitary filter banks on adder-based distributed arithmeticru_RU
dc.typeСтатьяru_RU
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