Searching for Optmal Synchronizing Sequences for Testng Logic Circuits

Cheremisinova, L. D.; Черемисинова Л. Д.

Full metadata record

DC Field	Value	Language
dc.contributor.author	Cheremisinova, L. D.	-
dc.contributor.author	Черемисинова Л. Д.	-
dc.date.accessioned	2015-02-24T12:47:27Z	-
dc.date.accessioned	2017-07-19T08:25:09Z	-
dc.date.available	2015-02-24T12:47:27Z	-
dc.date.available	2017-07-19T08:25:09Z	-
dc.date.issued	2011	-
dc.identifier.citation	Cheremisinova, L. D. Searching for Optmal Synchronizing Sequences for Testng Logic Circuits / L. D. Cheremisinova // Информационные технологии и системы 2011 (ИТС 2011) : материалы международной научной конференции, БГУИР, Минск, Беларусь, 26 октября 2011 г. = Information Technologies and Systems 2011 (ITS 2011) : Proceeding of The International Conference, BSUIR, Minsk, 26th October 2011 / редкол.: Л. Ю. Шилин [и другие]. – Минск : БГУИР, 2011. – C. 264-265.	ru_RU
dc.identifier.isbn	978-985-488-816-3	-
dc.identifier.uri	https://libeldoc.bsuir.by/handle/123456789/3292	-
dc.description.abstract	The problem under consideration is to find a synchronizing sequence for a logic network with memory. A novel method is proposed that is based on formulation of the task as Boolean satisfiability problem solved with any standard SAT solver. The developed method allows creating a Boolean equation presenting the problem in conjunctive normal form.	ru_RU
dc.language.iso	en	ru_RU
dc.publisher	БГУИР	ru_RU
dc.subject	conference materials	ru_RU
dc.subject	материалы конференций	ru_RU
dc.subject	integrated circuits	ru_RU
dc.subject	интегральные схемы	ru_RU
dc.subject	design automation	ru_RU
dc.subject	автоматизация проектирования	ru_RU
dc.subject	verification	ru_RU
dc.subject	верификация	ru_RU
dc.subject	testing logic circuits	ru_RU
dc.subject	тестирование логических схем	ru_RU
dc.title	Searching for Optmal Synchronizing Sequences for Testng Logic Circuits	ru_RU
dc.type	Article	ru_RU
Appears in Collections:	ИТС 2011