https://libeldoc.bsuir.by/handle/123456789/3292| Title: | Searching for Optmal Synchronizing Sequences for Testng Logic Circuits |
| Authors: | Cheremisinova, L. D. Черемисинова Л. Д. |
| Keywords: | conference materials;материалы конференций;integrated circuits;интегральные схемы;design automation;автоматизация проектирования;verification;верификация;testing logic circuits;тестирование логических схем |
| Issue Date: | 2011 |
| Publisher: | БГУИР |
| Citation: | Cheremisinova, L. D. Searching for Optmal Synchronizing Sequences for Testng Logic Circuits / L. D. Cheremisinova // Информационные технологии и системы 2011 (ИТС 2011) : материалы международной научной конференции, БГУИР, Минск, Беларусь, 26 октября 2011 г. = Information Technologies and Systems 2011 (ITS 2011) : Proceeding of The International Conference, BSUIR, Minsk, 26th October 2011 / редкол.: Л. Ю. Шилин [и другие]. – Минск : БГУИР, 2011. – C. 264-265. |
| Abstract: | The problem under consideration is to find a synchronizing sequence for a logic network with memory. A novel method is proposed that is based on formulation of the task as Boolean satisfiability problem solved with any standard SAT solver. The developed method allows creating a Boolean equation presenting the problem in conjunctive normal form. |
| URI: | https://libeldoc.bsuir.by/handle/123456789/3292 |
| ISBN: | 978-985-488-816-3 |
| Appears in Collections: | ИТС 2011 |
| File | Description | Size | Format | |
|---|---|---|---|---|
| Cheremisinova_Searching.PDF | 502.18 kB | Adobe PDF | View/Open |
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